{"id":210,"date":"2021-09-03T12:07:24","date_gmt":"2021-09-03T03:07:24","guid":{"rendered":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/?p=210"},"modified":"2022-05-31T10:25:44","modified_gmt":"2022-05-31T01:25:44","slug":"yuki-torigai","status":"publish","type":"post","link":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/member\/ob-og\/yuki-torigai\/","title":{"rendered":"\u9ce5\u98fc \u52c7\u5e0c (Yuki Torigai)"},"content":{"rendered":"\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"300\" height=\"225\" src=\"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-content\/uploads\/sites\/2\/2021\/09\/P10002321-300x225-1.jpg\" alt=\"\" class=\"wp-image-278\"\/><\/figure>\n\n\n\n<p>\u8da3\u5473\uff1a\u30b9\u30dd\u30fc\u30c4<\/p>\n\n\n\n<p><strong>\u7814\u7a76\u30c6\u30fc\u30de<\/strong><br>\u30fb\u5149\u518d\u69cb\u6210\u578b\u30b2\u30fc\u30c8\u30a2\u30ec\u30a4\u306e\u52d5\u7684\u6545\u969c\u691c\u51fa\u6a5f\u80fd\u306e\u7814\u7a76<\/p>\n\n\n\n<p style=\"font-size:25px\"><strong>\u696d\u7e3e<\/strong><\/p>\n\n\n\n<p><strong>\u8868\u5f70<\/strong><\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Winner of the Open League\u00a0in FPGA Design Contest 2014 AISO CUP,<br>T. Fujimori, M. Seo, K. Akagi, R. Moriwaki, T. Yoza, <strong>Y. Torigai<\/strong>, M. Watanabe,<br>International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, June,\u00a02014.<\/li><li>Champion of the Regulation League\u00a0in FPGA Design Contest 2014 AISO CUP,<br>T. Fujimori, M. Seo, K. Akagi, R. Moriwaki, T. Yoza, <strong>Y. Torigai<\/strong>, M. Watanabe,<br>International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, June,\u00a02014.<\/li><li>HDL Champion of the Regulation League\u00a0in FPGA Design Contest 2014 AISO CUP,<br>T. Fujimori, M. Seo, K. Akagi, R. Moriwaki, T. Yoza, <strong>Y. Torigai<\/strong>, M. Watanabe,<br>International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, June,\u00a02014.<\/li><li>\u5b66\u9577\u8cde\u3000\u53d7\u8cde(ICFPT Design Competition\u512a\u52dd\u306e\u70ba)<\/li><li>T. Yoza, R. Moriwaki,\u00a0<strong>Y. Torigai,<\/strong>\u00a0Y. Kamikubo, T. Kubota, T. Watanabe, T. Fujimori, H. Ito, M. Seo, K. Akagi, Y. Yamaji, M. Watanabe,<br>First Place in ICFPT Design Competition 2013,Dec. 2013<\/li><li>T. Yoza, R. Moriwaki,\u00a0<strong>Y. Torigai,<\/strong>\u00a0Y. Kamikubo, T. Kubota, T. Watanabe, T. Fujimori, H. Ito, M. Seo, K. Akagi, Y. Yamaji, M. Watanabe,<br>HDL Champion in ICFPT Design Competition 2013,Dec. 2013.<\/li><li>\u68ee\u8107\u70c8\uff0c\u4f59\u5ea7\u8cb4\u5fd7\uff0c\u6e21\u908a\u8cb4\u5f18\uff0c<strong>\u9ce5\u98fc\u52c7\u5e0c<\/strong>\uff0c\u4e0a\u7aaa\u52c7\u8cb4\uff0c\u5c71\u5730\u52c7\u4e00\u90ce\uff0c\u7aaa\u7530\u8cb4\u4e4b\uff0c\u4f0a\u85e4\u5b8f\u5e78\uff0c\u6e21\u908a\u5b9f<br>\u7b2c3\u56de\u76f8\u78ef\u79c0\u592b\u676f FPGA\u30c7\u30b6\u30a4\u30f3\u30b3\u30f3\u30c6\u30b9\u30c8 \u512a\u52dd 2013\u5e749\u6708<\/li><li>\u5b66\u9577\u8868\u5f702012\u5e74\u5ea6, \u6e21\u908a\u7814\u7a76\u5ba4<\/li><li>\u68ee\u8107\u3001\u4f59\u5ea7\u3001\u4e0a\u7aaa\u3001<strong>\u9ce5\u98fc<\/strong>\u3001\u8c37\u5ddd\u3001\u7aaa\u7530\u3001\u4f0a\u85e4\u3001\u767d\u6a4b\u3001\u6e21\u908a<br>FPT 2012 Design Competition \u2014 Connect6, \u512a\u52dd, 2012<\/li><li>\u68ee\u8107\u3001\u4f59\u5ea7\u3001\u6e21\u908a\u3001\u4e0a\u7aaa\u3001<strong>\u9ce5\u98fc<\/strong>\u3001\u767d\u6a4b\u3001\u4f0a\u85e4\u3001\u7aaa\u7530\u3001\u8c37\u5ddd\u3001\u5c71\u5730\u3001\u9752\u5c71\u3001\u702c\u5c3e\u3001\u6e21\u908a<br>HEART\u56fd\u969b\u4f1a\u8b70-connect6\u512a\u52dd,2012<\/li><li>\u5b66\u9577\u8868\u5f702011\u5e74\u5ea6, \u6e21\u908a\u7814\u7a76\u5ba4<\/li><li>\u793e\u4f1a\u4eba\u57fa\u790e\u529b\u80b2\u6210\u30b0\u30e9\u30f3\u30d7\u30ea2012\u6c7a\u52dd\u5927\u4f1a, \u6e96\u5927\u8cde<\/li><li>FPT 2011 Design Competition \u2014 Connect6, \u512a\u52dd, 2011<\/li><li>\u793e\u4f1a\u4eba\u57fa\u790e\u529b\u80b2\u6210\u30b0\u30e9\u30f3\u30d7\u30ea2012\u95a2\u6771\u5730\u533a\u4e88\u9078\u5927\u4f1a, \u512a\u79c0\u8cde<\/li><li>\u6e21\u908a\u8cb4\u5f18,\u68ee\u8107\u70c8,\u5c71\u5730\u52c7\u4e00\u90ce,\u4e0a\u7aaa\u52c7\u8cb4,<strong>\u9ce5\u98fc\u52c7\u5e0c<\/strong>,\u4ec1\u5e73\u512a\u57fa,\u4f59\u5ea7\u8cb4\u5fd7,\u4e0a\u91ce\u7531\u7f8e\u5b50,\u9752\u5c71\u88d5\u53f8,\u6e21\u908a\u5b9f,<br>\u7b2c1\u56de \u76f8\u78ef\u79c0\u592b\u676f FPGA\u30c7\u30b6\u30a4\u30f3\u30b3\u30f3\u30c6\u30b9\u30c8\u3000\u512a\u52dd, 2011<\/li><\/ol>\n\n\n\n<p><strong>\u5b66\u8853\u8ad6\u6587<\/strong><\/p>\n\n\n\n<p><strong>\u56fd\u969b\u5b66\u4f1a<\/strong><\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>T. Yoza, R. Moriwaki,&nbsp;<strong>Y. Torigai,<\/strong>&nbsp;Y. Kamikubo, T. Kubota, T. Watanabe, T. Fujimori, H. Ito, M. Seo, K. Akagi, Y. Yamaji, M. Watanabe,<br>\u201cFPGA Blokus Duo Solver using a massively parallel architecture,\u201d<br>International Conference on Field-Programmable Technology, pp. 494-497, Kyoto, Japan, Dec.,&nbsp;<strong>2013<\/strong>.<br>DOI:&nbsp;<a href=\"https:\/\/doi.org\/10.1109\/FPT.2013.6718426\">10.1109\/FPT.2013.6718426<\/a>&nbsp;(IEEE Xplore)<\/li><li>R. Moriwaki, T. Yoza, Y. Kamikubo,&nbsp;<strong>Y. Torigai,<\/strong>&nbsp;A. Tanigawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe,<br>\u201cA 7-depth search FPGA Connect6 Solver,\u201d<br>International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, pp. 95-98, Edinburgh, United Kingdom, June,&nbsp;<strong>2013<\/strong>.<\/li><li>R. Moriwaki, T. Yoza, Y. Kamikubo,&nbsp;<strong>Y. Torigai,<\/strong>&nbsp;T. Watanabe, Y. Aoyama, M. Seo, M. Watanabe,<br>\u201cFPGA Connect6 Solver with Hardware Sort Units,\u201d<br>International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, pp. 163-166, Okinawa, Japan, May,&nbsp;<strong>2012<\/strong>.<\/li><li>T. Watanabe, R. Moriwaki, Y. Yamaji, Y. Kamikubo,&nbsp;<strong>Y. Torigai,<\/strong>&nbsp;Y. Nihira, T. Yoza, Y. Ueno, Y. Aoyama, M. Watanabe,<br>\u201cAn FPGA Connect6 Solver with a Two-Stage Pipelined Evaluation,\u201d<br>IEEE International Conference on Field-Programmable Technology, CD-ROM, New Delhi, India, Dec.,&nbsp;<strong>2011<\/strong>.<br>DOI:&nbsp;<a href=\"https:\/\/doi.org\/10.1109\/FPT.2011.6133249\">10.1109\/FPT.2011.6133249<\/a>&nbsp;(IEEE Xplore)<\/li><li><strong>Y. Torigai,<\/strong>&nbsp;M. Watanabe,<br>\u201cTriple module redundancy scheme on an optically reconfigurable gate array,\u201d<br>International SoC Design Conference, pp. 250 \u2013 253, Jeju, Korea, Nov.,&nbsp;<strong>2011<\/strong>.<br>DOI:&nbsp;<a href=\"https:\/\/doi.org\/10.1109\/ISOCC.2011.6138757\">10.1109\/ISOCC.2011.6138757<\/a>&nbsp;(IEEE Xplore)<\/li><\/ol>\n\n\n\n<p><strong>\u56fd\u5185\u5b66\u4f1a<\/strong><\/p>\n\n\n\n<ol class=\"wp-block-list\"><li><strong>\u9ce5\u98fc\u52c7\u5e0c<\/strong>\uff0c\u6e21\u908a\u5b9f\uff0c\u300c\u5149\u518d\u69cb\u6210\u578b\u30b2\u30fc\u30c8\u30a2\u30ec\u30a4\u3078\u306e\u4e09\u91cd\u56de\u8def\u5b9f\u88c5\u300d<br>\u96fb\u5b50\u60c5\u5831\u901a\u4fe1\u5b66\u4f1a\u6771\u6d77\u652f\u90e8\u5352\u696d\u7814\u7a76\u767a\u8868\u4f1a\uff0c\u5c90\u961c\u5927\u5b66\uff0c3\u6708\uff0c2012.<\/li><li><strong>\u9ce5\u98fc\u52c7\u5e0c<\/strong>\uff0c\u6e21\u908a\u5b9f\uff0c\u300c\u5149\u518d\u69cb\u6210\u578b\u30b2\u30fc\u30c8\u30a2\u30ec\u30a4\u3078\u306e\u4e09\u91cd\u56de\u8def\u5b9f\u88c5\u300d\uff0c<br>\u96fb\u6c17\u95a2\u4fc2\u5b66\u4f1a\u6771\u6d77\u652f\u90e8\u9023\u5408\u5927\u4f1a\uff0cCD-ROM, \u4e09\u91cd\u5927\u5b66\uff0c9\u6708\uff0c2011\uff0e<\/li><\/ol>\n\n\n\n<p><strong>\u6240\u5c5e\u5b66\u4f1a<\/strong><br>\u30fbIEEE\u3000\u3000\u3000\u5b66\u751f\u4f1a\u54e1<br>\u30fb\u96fb\u5b50\u60c5\u5831\u901a\u4fe1\u5b66\u4f1a\u3000\u3000\u3000\u5b66\u751f\u4f1a\u54e1<\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u8da3\u5473\uff1a\u30b9\u30dd\u30fc\u30c4 \u7814\u7a76\u30c6\u30fc\u30de\u30fb\u5149\u518d\u69cb\u6210\u578b\u30b2<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"template-fullwidth.php","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[3,4],"tags":[],"class_list":["post-210","post","type-post","status-publish","format-standard","hentry","category-ob-og","category-member"],"jetpack_sharing_enabled":true,"jetpack_featured_media_url":"","_links":{"self":[{"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/posts\/210","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/comments?post=210"}],"version-history":[{"count":4,"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/posts\/210\/revisions"}],"predecessor-version":[{"id":483,"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/posts\/210\/revisions\/483"}],"wp:attachment":[{"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/media?parent=210"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/categories?post=210"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.rs.cs.okayama-u.ac.jp\/shizuoka-watanabe-lab\/wp-json\/wp\/v2\/tags?post=210"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}